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VGADB(6)                         Games Manual                         VGADB(6)

       vgadb - VGA controller and monitor database

       The VGA database, /lib/vgadb, consists of two parts, the first describ-
       ing how to identify  and  program  a  VGA  controller  and  the  second
       describing the timing parameters for known monitors to be loaded into a
       VGA controller to give a particular resolution and refresh rate.   Con-
       ventionally,  at system boot, the program aux/vga (see vga(8)) uses the
       monitor type in /env/monitor, the display resolution  in  /env/vgasize,
       and  the  VGA controller information in the database to find a matching
       monitor entry and initialize the VGA controller accordingly.

       The file comprises multi-line entries made up of attribute/value  pairs
       of  the  form  attr=value  or  sometimes just attr.  Each line starting
       without white space starts a new entry.  Lines starting with # are com-

       The  first  part of the database, the VGA controller identification and
       programming information, consists of a number of entries with attribute
       ctlr  and  no  value.   Within  one  of  these  entries  the  following
       attributes are meaningful:

       nnnnn  an offset into the  VGA  BIOS  area.   The  value  is  a  string
              expected  to  be  found there that will identify the controller.
              For example, 0xC0068="#9GXE64 Pro" would identify a #9GXEpro VGA
              controller  if  the  string #9GXE64 Pro was found in the BIOS at
              address  0xC0068.   There  may  be  more  than  one   identifier
              attribute per controller.  If a match cannot be found, the first
              few bytes of the BIOS are printed to help identify the card  and
              create a controller entry.

       ctlr   VGA  controller  chip type.  This must match one of the VGA con-
              troller types known to /dev/vgactl (see vga(3))  and  internally
              to aux/vga.  Currently, clgd542x, et4000, mach32, mach64, s3801,
              s3805, s3928, vision864, and vision964 are recognized.

       ramdac RAMDAC controller type.  This must match one of the types  known
              internally   to   aux/vga.    Currently   att20c491,  att20c492,
              att21c498, bt485, sc15025, stg1702,  tvp3020,  and  tvp3025  are

       clock  clock  generator  type.   This must match one of the types known
              internally to aux/vga.  Currently icd2061a,  ics2494,  ics2494a,
              s3clock, and tvp3025clock are recognized.

       hwgc   hardware graphics cursor type.  This must match one of the types
              known to  /dev/vgactl  and  internally  to  aux/vga.   Currently
              bt485hwgc, s3hwgc, et4000hwgc, and tvp3020hwgc are recognized.

       link   This  must  match  one of the types known internally to aux/vga.
              Currently vga and ibm8514 are recognized.  The type vga  handles
              generic VGA functions and should almost always be included.  The
              type Ibm8514 handles basic graphics  accelerator  initialization
              on controllers such as the S3 family of GUI chips.

       The clock, ctlr, link, and ramdac values can all take an extension fol-
       lowing a '-' that can be used as a speed-grade or subtype; matching  is
       done  without the extension.  For example, ramdac=stg1702-135 indicates
       the STG1702 RAMDAC  has  a  maximum  clock  frequency  of  135MHz,  and
       clock=ics2494a-324  indicates  that  the  frequency  table numbered 324
       should be used for the ICS2494A clock generator.

       The functions internal to aux/vga corresponding  to  the  clock,  ctlr,
       link,  and ramdac values will be called in the order given for initial-
       ization.  Sometimes the clock should be set before the RAMDAC  is  ini-
       tialized,  for  example, depending on the components used.  In general,
       link=vga will always be first and, if appropriate, link=ibm8514 will be

       The entries in the second part of /lib/vgadb have as attribute the name
       of a monitor type and the value is conventionally a resolution  in  the
       form  XxYxZ,  where X, Y, and Z are numbers representing width, height,
       and depth in pixels.  The monitor type (i.e. entry) include has special
       properties,  described  below and shown in the examples.  The remainder
       of the entry contains timing information for  the  desired  resolution.
       Within one of these entries the following attributes are meaningful:

       clock  the  video  dot-clock frequency in MHz required for this resolu-
              tion.  The value 25.175 is known internally  to  vga(8)  as  the
              baseline VGA clock rate.

       shb    start horizontal blanking, in character clocks.

       ehb    end horizontal blanking, in character clocks.

       ht     horizontal total, in character clocks.

       vrs    vertical refresh start, in character clocks.

       vre    vertical refresh end, in character clocks.

       vt     vertical total, in character clocks.

       hsync  horizontal sync polarity.  Value must be '+' or '-'.

       vsync  vertical sync polarity.  Value must be + or -.

              interlaced mode.  Only value v is recognized.

       alias  continue,  replacing the alias line by the contents of the entry
              whose attribute is given as value.

              continue, replacing this include line by  the  contents  of  the
              previously  defined  include  monitor  type with matching value.
              (See the examples.)  Any non-zero attributes  already  set  will
              not  be overwritten.  This is used to save duplication of timing
              information.  Note that value is not parsed, it is only used  as
              a  string  to  identify  the previous include=value monitor type

       The values given for shb, ehb, ht, vrs, vre, vt, hsync, and  vsync  are
       beyond  the  scope  of  this  manual page.  See the book by Ferraro for

       Basic ctlr entry for a laptop which is only capable of a 640x480x1 res-

       ctlr                          # AT&T Safari NSX20
            0xE0030="PhoenixVIEW(tm) VGA-Compatible BIOS Version"

       A  more complex entry. Note the extensions on the clock, ctlr, and ram-
       dac attributes. The order here is important:  the  RAMDAC  clock  input
       must  be  initialized  before the RAMDAC itself. The clock frequency is
       selected by the ET4000 chip.

       ctlr                          # Hercules Dynamite Power
            0xC0076="Tseng Laboratories, Inc. 03/04/94 V8.00N"

       Monitor entry for type vga (the default monitor type  used  by  vga(8))
       and resolution 640x480x[18].

       include = 640x480@60Hz                  # 60Hz, 31.5KHz
            shb=664 ehb=760 ht=800
            vrs=491 vre=493 vt=525

       vga = 640x480x1                         # 60Hz, 31.5KHz
       vga = 640x480x8                         # 60Hz, 31.5KHz

       Entries for multisync monitors with video bandwidth up to 65MHz.

       # Multisync monitors with video bandwidth up to 65MHz.
       multisync65 = 1024x768x1                # 60Hz, 48.4KHz
       multisync65 = 1024x768x8                # 60Hz, 48.4KHz
       multisync65 = 1024x768x1i               # 87Hz, 35.5KHz (interlaced)
       multisync65 = 1024x768x8i               # 87Hz, 35.5KHz (interlaced)

       Note how this builds on the existing vga entries.


       ndb(2), vga(3), ndb(6), b.com(8), vga(8)
       Richard  E.  Ferraro,  Programming  Guide to the EGA, VGA and Super VGA
       Cards, Third Edition

       The mach32 and mach64 controllers are programmed only in VGA mode,  not
       accelerated mode, so are limited to a maximum resolution of 10247688.

       Adding  a new monitor is usually fairly straightforward, as most modern
       monitors are multisync and the only interesting parameter is the  maxi-
       mum  video  bandwidth.  Once the timing parameters are worked out for a
       particular maximum video bandwidth as in the example  above,  an  entry
       for a new monitor with that limit is simply

       # Sony CPD-1304
       # Horizontal timing:
       #    Allowable frequency range: 28-50KHz
       # Vertical timing:
       #    Allowable frequency range: 50-87Hz

       Even  this  is not necessary, as the monitor type could simply be given
       as multisync65.

       While the use of this database formalizes the steps needed to program a
       VGA  controller, unless you are very lucky and all the important compo-
       nents on a new VGA controller card are interconnected in the  same  way
       as  an  existing entry, adding a new entry requires adding new internal
       types to vga(8).

       At a minimum you will need the data sheets for the VGA controller chip,
       the  RAMDAC  and  the  clock generator.  You will also need to know how
       these components interact.  For example, a common combination is an  S3
       86C928  VGA chip with an ICD2061A clock generator. The ICD2061A is usu-
       ally loaded by clocking a serial bit-stream out of one  of  the  86C928
       registers.   Similarly,  the  RAMDAC may have an internal clock-doubler
       and/or pixel-multiplexing modes, in which case both the clock generator
       and VGA chip must be programmed accordingly.