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 make(1)							     make(1)

      make - maintain, update, and regenerate groups of programs

      make [-f makefile] [-bBdeiknpPqrsStuw] [macro_name=value] [names]

    Makefile Structure
      A makefile can contain four different kinds of lines: target lines,
      shell command lines, macro definitions, and include lines.

      Target lines consist of a blank-separated, non-null list of targets,
      followed by a colon (:) or double colon (::), followed by a (possibly
      null) list of prerequisite files called dependents.  Pattern Matching
      Notation (see regexp(5)) is supported for the generation of file names
      as dependents.

      Text following a semicolon (;) on a target line, and all following
      lines that begin with a tab are shell commands to be executed to
      update the target (see the Environment section below about SHELL).
      The first line that does not begin with a tab or # begins a new target
      definition, macro definition, or include line.  Shell commands can be
      continued across lines by using a <backslash><new-line> sequence.

      Target lines with their associated command lines are called rules.

      Lines of the form string1 = string2 are macro definitions.  Macros can
      be defined anywhere in the makefile, but are usually grouped together
      at the beginning.	 string1 is the macro name; string2 is the macro
      value.  string2 is defined as all characters up to a comment character
      or an unescaped new-line.	 Spaces and tabs immediately to the left and
      right of the = are ignored.  Subsequent appearances of $(string1)
      anywhere in the makefile (except in comments) are replaced by string2.
      The parentheses are optional if a single character macro name is used
      and there is no substitute sequence.  An optional substitute sequence,
      $(string1 [:subst1=[subst2]]) can be specified, which causes all
      nonoverlapping occurrences of subst1 at the end of substrings in the
      value of string1 to be replaced by subst2.  Substrings in a macro
      value are delimited by blanks, tabs, new-line characters, and
      beginnings of lines.  For example, if

	   OBJS = file1.o file2.o file3.o



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 make(1)							     make(1)

      evaluates to

	   file1.c file2.c file3.c

      Macro values can contain references to other macros (see WARNINGS):

	   ONE =1

	   TWELVE = $(ONE)2

      The value of $(TWELVE) is set to $(ONE)2 but when it is used in a
      target, command, or include line, it is expanded to 12.  If the value
      of ONE is subsequently changed by another definition further down in
      the makefile or on the command line, any references to $(TWELVE)
      reflect this change.

      Macro definitions can also be specified on the command line and
      override any definitions in the makefile.

      (XPG4 only.  Macros on the command line are added to the MAKEFLAGS
      environment variable.  Macros defined in the MAKEFLAGS environment
      variable, but without any command line macro, adds the macro to the
      environment overwriting any existing environment variable of the same

      Certain macros are automatically defined for make (see Built-in
      Macros).	See the Environment section for a discussion of the order in
      which macro definitions are treated.

      The value assigned to a macro can be overridden by a conditional macro
      definition.  A conditional macro definition takes on the form target
      := string1 = string2.  When the target line associated with target is
      being processed, the macro value specified in the conditional macro
      definition is in effect.	If string1 is previously defined, the new
      value of string1 will override the previous definition.  The new value
      of string1 takes effect when target or any dependents of target are
      being processed.

      If the string include appears as the first seven letters of a line in
      a makefile, and is followed by one or more space or tab characters,
      the rest of the line is assumed to be a file name and is read and
      processed by the current invocation of make as another makefile after
      any macros in the filename have been expanded.

      The default behaviour of make is to use .DEFAULT built-in target, if
      target does not have explicit commands associated with it and .DEFAULT
      target is defined. See the Built-In Targets Section.

    General Description
      make executes commands previously placed in a makefile to update one

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 make(1)							     make(1)

      or more target names.  Target names are typically names of programs.
      If no -f option is specified, the filenames makefile, Makefile,
      s.makefile, SCCS/s.makefile, s.Makefile and SCCS/s.Makefile are tried
      in that order.  If -f - is specified, the standard input is used.
      More than one -f option can be specified.	 The makefile arguments are
      processed in the order specified.	 A space between the -f and the
      filename must be present, and multiple makefile names must each have
      their own -f option preceding them.  The contents of a makefile
      override the built-in rules and macros if they are present.

      If no target names are specified on the command line, make updates the
      first target in the (first) makefile that is not an inference rule.  A
      target is updated only if it depends on files that are newer than the
      target.  Missing files are deemed to be out-of-date.  All dependents
      of a target are recursively updated, if necessary, before the target
      is updated.  This effects a depth-first update of the dependency tree
      for the target.

      If a target does not have any dependents specified after the separator
      on the target line (explicit dependents), any shell commands
      associated with that target are executed if the target is out-of-date.

      A target line can have either a single or double colon between the
      target name or names and any explicit dependent names.  A target name
      can appear on more than one target line, but all of those lines must
      be of the same (single- or double-colon) type.  For the usual single-
      colon case, at most one of these target lines can have explicit
      commands associated with it.  If the target is out-of-date with any of
      its dependents on any of the lines, the explicit commands are
      executed, if they are specified, or else a default rule can be
      executed.	 For the double-colon case, explicit commands can be
      associated with more than one of the target lines containing the
      target name; if the target is out-of-date with any of the dependents
      on a particular line, the commands for that line are executed.  A
      built-in rule may also be executed.

      Target lines and their associated shell command lines are also
      referred to as rules.  Hash marks (#) and new-line characters surround
      comments anywhere in the makefile except in rules.  Comments in the
      rules depend on the setting of the SHELL macro.

      The following makefile says that pgm depends on two files: a.o and
      b.o, and that they in turn depend on their corresponding source files
      (a.c and b.c) and a common file incl.h:

	   OBJS = a.o b.o

	   pgm: $(OBJS)
	       cc $(OBJS) -o pgm

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 make(1)							     make(1)

	   a.o: incl.h a.c
	       cc -c a.c

	   b.o: incl.h b.c
	       cc -c b.c

      Command lines are executed one at a time, each by its own shell.	Each
      command line can have one or more of the following prefixes: -, @, or
      +.  These prefixes are explained below.

      Commands returning non-zero status normally terminate make.  The -i
      option or the presence of the special target .IGNORE in the makefile
      cause make to continue executing the makefile regardless of how many
      command lines cause errors, although the error messages are still
      printed on standard output.  If - is present at the beginning of a
      command line, any error returned by that line is printed to standard
      output but make does not terminate.  The prefix - can be used to
      selectively ignore errors in a makefile.	If the -k option is
      specified and a command line returns an error status, work is
      abandoned on the current target, but continues on other branches that
      do not depend on that target.  If the -k option is present in the
      MAKEFLAGS environment variable, processing can be returned to the
      default by specifying the -S option.

      The -n option specifies printing of a command line without execution.
      However, if the command line has the string $(MAKE) or ${MAKE} in it
      or + as a prefix, the line is always executed (see discussion of the
      MAKEFLAGS macro under Environment).  The -t (touch) option updates the
      modified date of a file without executing any commands.

      A command line is normally printed before it is executed, but if the
      line has a @ at the beginning, printing is suppressed.  The -s option
      or the presence of the special target .SILENT: in the makefile
      suppresses printing of all command lines.	 The @ can be used to
      selectively turn off printing.  Everything printed by make (except the
      initial tab) is passed directly to the shell without alteration.

	   echo a\



      just as the shell would.

      The -b option allows old makefiles (those written for the old version
      of make) to run without errors.  The old version of make assumed that
      if a target did not have any explicit commands associated with it, the
      user intended the command to be null, and would not execute any

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 make(1)							     make(1)

      .DEFAULT rule that might have been defined.  The current version of
      make operates in this mode by default.  However, the current version
      of make provides a -B option which turns this mode off so that if a
      target does not have explicit commands associated with it and a
      .DEFAULT rule is defined, the .DEFAULT rule is executed.	Note that
      the -b and -B options have no effect on the search and possible
      location and execution of an appropriate inference rule for the
      target.  The search for a built-in inference rule other than .DEFAULT
      is always performed.

      The signals SIGINT, SIGQUIT, SIGHUP, and SIGTERM (see signal(5)) cause
      the target to be deleted unless the target depends on the special name

      The following is a brief description of all options and some special
      names.  Options can occur in any order.  They can be specified
      separately, or together with one -, except for the -f option.

      -b	     Compatibility mode for old (Version 7) makefiles.	This
		     option is turned on by default.

      -B	     Turn off compatibility mode for old (Version 7)

      -d	     Debug mode.  Print out detailed information on files
		     and times examined.  (This is very verbose and is
		     intended for debugging the make command itself.)

      -e	     Environment variables override assignments within
		     makefiles .

      -f  makefile   Description file name, referred to as the makefile.  A
		     file name of - denotes the standard input.	 The
		     contents of the makefile override the built-in rules
		     and macros if they are present.  Note that the space
		     between -f and makefile must be present.  Multiple
		     instances of this option are allowable (except for -f
		     -), and are processed in the order specified.

      -i	     Ignore error codes returned by invoked commands.  This
		     mode is also entered if the special target name .IGNORE
		     appears in the makefile.

      -k	     When a command returns nonzero status, abandon work on
		     the current entry, but continue on other branches that
		     do not depend on that target.  This is the opposite of
		     -S.  If both -k and -S are specified, the last one
		     specified is used.

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 make(1)							     make(1)

      -n	     No execute mode.  Print commands, but do not execute
		     them.  Even lines beginning with an @ are printed.
		     However, lines that contain the string $(MAKE) or
		     ${MAKE} or that have + as a prefix to the command are

      -p	     Write to standard output the complete set of macro
		     definitions and target descriptions.

      -P	     Update in parallel more than one target at a time. The
		     number of targets updated concurrently is determined by
		     the environment variable PARALLEL and the presence of
		     .MUTEX directives in make file.

      -q	     Question.	The make command returns a zero or non-zero
		     status code, depending on whether the target file is or
		     is not up-to-date.	 Targets are not updated with this

      -r	     Clear suffix list and do not use the built-in rules.

      -s	     Silent mode.  Command lines are not printed to standard
		     output before their execution.  This mode is also
		     entered if the special target name .SILENT appears in
		     the makefile.

      -S	     Terminate if an error occurs while executing the
		     commands to bring a target up-to-date.  This is the
		     default and the opposite of -k.  If both -k and -S are
		     specified, the last one given is used.  This enables
		     overriding the presence of the k flag in the MAKEFLAGS
		     environment variable.

      -t	     Touch the target files (causing them to be up-to-date)
		     rather than issue the usual commands.

      -u	     Unconditionally make the target, ignoring all

      -w	     Suppress warning messages. Fatal messages will not be

		     Zero or more command line macro definitions can be
		     specified.	 See the Macros section.

      [names]	     Zero or more target names that appear in the makefile.
		     Each target so specified is updated by make.  If no
		     names are specified, make updates the first target in
		     the makefile that is not an inference rule.

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 make(1)							     make(1)

    Parallel Make
      If make is invoked with the -P option, it tries to build more than one
      target at a time, in parallel.  (This is done by using the standard
      UNIX system process mechanism which enables multiple processes to run
      simultaneously.)	For the makefile shown in the example in the
      previous section, it would create processes to build a.o and b.o in
      parallel.	 After these processes were complete, it would build pgm.

      The number of targets make will try to build in parallel is determined
      by the value of the environment variable PARALLEL.  If -P is invoked,
      but PARALLEL is not set, then make will try to build no more than two
      targets in parallel.

      You can use the .MUTEX directive to serialize the updating of some
      specified targets.  This is useful when two or more targets modify a
      common output file, such as when inserting modules into an archive or
      when creating an intermediate file with the same name, as is done by
      lex and yacc.  If the makefile in the previous section contained a
      .MUTEX directive of the form

	   .MUTEX: a.o b.o

      it would prevent make from building a.o and b.o in parallel.

      All variables defined in the environment (see environ(5)) are read by
      make and are treated and processed as macro definitions, with the
      exception of the SHELL environment variable which is always ignored.
      The value of the SHELL environment variable will not be used as a
      macro and will not be modified by defining the SHELL macro in a
      makefile or on the command line.	Variables with no definition or
      empty string definitions are included by make.

      There are four possible sources of macro definitions which are read in
      the following order: internal (default), current environment, the
      makefile(s), and command line.  Because of this order of processing,
      macro assignments in a makefile override environment variables.  The
      -e option allows the environment to override the macro assignments in
      a makefile.  Command-line macro definitions always override any other

      The MAKEFLAGS environment variable is processed by make on the
      assumption that it contains any legal input option (except -f, -p, and
      -d) defined for the command line.	 The MAKEFLAGS variable can also be
      specified in the makefile.

      (XPG4 only.  MAKEFLAGS in the makefile replaces the MAKEFLAGS
      environment variable. Command line options have precedence over
      MAKEFLAGS environment variable.)

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 make(1)							     make(1)

      If MAKEFLAGS is not defined in either of these places, make constructs
      the variable for itself, puts the options specified on the command
      line and any default options into it, and passes it on to invocations
      of commands.  Thus, MAKEFLAGS always contains the current input
      options.	This proves very useful for recursive makes.  Even when the
      -n option is specified, command lines containing the string $(MAKE) or
      ${MAKE} are executed; hence, one can perform a make -n recursively on
      an entire software system to see what would have been executed.  This
      is possible because the -n is put into MAKEFLAGS and passed to the
      recursive invocations of $(MAKE) or ${MAKE}.  This is one way of
      debugging all of the makefiles for a software project without actually
      executing any of the commands.

      Each of the commands in the rules is given to a shell to be executed.
      The shell used is the shell command interpreter (see sh(1)), or the
      one specified in the makefile by the SHELL macro.	 To ensure the same
      shell is used each time a makefile is executed, the line:


      or a suitable equivalent should be put in the macro definition section
      of the makefile.

      Target and/or dependent names often have suffixes.  Knowledge about
      certain suffixes is built into make and used to identify appropriate
      inference rules to be applied to update a target (see the section on
      Inference Rules).	 The current default list of suffixes is:

	   .o .c .c~ .C .C~ .cxx .cxx~ .cpp .cpp~ .cc .cc~
	   .y .y~ .l .l~ .L .L~ .Y .Y~ .s .s~ .sh .sh~
	   .h .h~ .H .H~  .p .p~ .f .f~ .r .r~

      These suffixes are defined as the dependents of the special built-in
      target .SUFFIXES.	 This is done automatically by make.

      Additional suffixes can be specified in a makefile as the dependents
      list for .SUFFIXES.  These additional values are added to the default
      values.  Multiple suffix lists accumulate.  The order of the suffix
      list is significant (see the Inference Rules section).  If the user
      wishes to change the order of the suffixes, he must first define
      .SUFFIXES with a null dependent list, which clears the current value
      for .SUFFIXES, and then define .SUFFIXES with the suffixes in the
      desired order.  The list of suffixes built into make on any machine
      can be displayed by:

	   make -fp - 2>&gt&gt&gt;/dev/null <&lt&lt&lt;/dev/null

      The list of built-in suffixes incorporated with the definitions in a
      given makefile called mymakefile can be displayed by:

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 make(1)							     make(1)

	   make -fp mymakefile 2>&gt&gt&gt;/dev/null <&lt&lt&lt;/dev/null

    Inference Rules
      Certain target or dependent names (such as those ending with .o) have
      inferable dependents such as .c and .s, etc.  If no update commands
      for such a name appear in the makefile, and if an inferable dependent
      file exists, that dependent file is compiled to update the target.  In
      this case, make has inference rules that allow building files from
      other files by examining the suffixes and determining an appropriate
      inference rule to use.  There are currently default inference rules
      defined for:

      Single Suffix Rules

		    .c .c~
		    .C .C~ .cxx .cxx~ .cpp .cpp~ .cc .cc~
		    .sh .sh~
		    .p .p~
		    .f .f~
		    .r .r~

      Double Suffix Rules

		    .c.o .c~.o .c~.c .c.a .c~.a
		    .C.o .C~.o .C~.C .C.a .C~.a
		    .cxx.o .cxx~.o .cxx~.cxx .cxx.a .cxx~.a
		    .cpp.o .cpp~.o .cpp~.cpp .cpp.a .cpp~.a
		    .cc.o .cc~.o .cc~.cc .cc.a .cc~.a
		    .s.o .s~.o .s~.a
		    .p.o .p~.o .p~.p .p.a .p~.a
		    .f.o .f~.o .f~.f .f.a .f~.a
		    .r.o .r~.o .r~.r .r.a .r~.a
		    .y.o .y~.o .y.c .y~.c
		    .l.o .l~.o .l.c
		    .h~.h  .H~.H .hxx~.hxx .hpp~.hpp
		    .C.o .C~.o .C.a .C~.a
		    .L.C .L.o .L~.C .L~.L .L~.o
		    .Y.C .Y.o .Y~.C .Y~.Y .Y~.o

      Double suffix inference rules (.c.o) define how to build x.o from x.c.
      Single suffix inference rules (.c) define how to build x from x.c.  In
      effect, the first suffix is null.	 Single suffix rules are useful for
      building targets from only one source file; e.g., shell procedures and
      simple C programs.

      A tilde in the above rules refers to an SCCS file (see sccsfile(4)).
      Thus, the rule .c~.o would transform an SCCS C source file into an
      object file (.o).	 Since the s.  of the SCCS files is a prefix, it is
      incompatible with make's suffix point-of-view.  Hence, the tilde is a
      way of changing any file reference into an SCCS file reference.

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 make(1)							     make(1)

      A rule to create a file with suffix .o from a file with suffix .c is
      specified as an entry with .c.o as the target and no dependents.
      Shell commands associated with the target define the rule for making a
      .o file from a .c file.  Any target name that has no slashes in it and
      starts with a dot is identified as an inference (implicit) rule
      instead of a target (explicit) rule.  Targets with one dot are single
      suffix inference rules; targets with two dots are double suffix
      inference rules.	Users can, in a makefile, define additional
      inference rules and either redefine or cancel default inference rules.

      The default inference rule for changing a .c file into a .o file might
      look like this:

	  $(CC) $(CFLAGS) -c $<&lt&lt&lt;

      and the default inference rule for changing a yacc file to a C object
      file might look like this:

	       $(YACC) $(YFLAGS) $<&lt&lt&lt;
	       $(CC) $(CFLAGS) -c y.tab.c
	       rm y.tab.c
	       mv y.tab.o $@

      Certain macros are used in the default inference rules to permit the
      inclusion of optional matter in any resulting commands.  For example,
      CFLAGS, LDFLAGS, and YFLAGS are used for compiler options to cc(1),
      lex(1), and yacc(1), respectively.  LDFLAGS is commonly used to
      designate linker/loader options.	These macros are automatically
      defined by make but can be redefined by the user in the makefile.

      The macro LIBS is, by convention, used to specify the order of
      inclusion of any special libraries during the linking phase of
      compilation.  To specify a particular order of inclusion for a
      particular set of libraries, the existing single suffix rule for a .c

	   $(CC) $(CFLAGS) $<&lt&lt&lt; $(LDFLAGS) -o $@

      can be redefined as

	   $(CC) $(CFLAGS) $<&lt&lt&lt; $(LDFLAGS) -o $@ $(LIBS)

      as well as defining LIBS in the makefile.

      There are also some special built-in macros used in the inference
      rules (@, <&lt&lt&lt;).  See the Built-in Macros section.

      If a target does not have explicit dependents, or if a dependent does
      not also have a target that matches it with associated explicit rules,

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 make(1)							     make(1)

      make looks for the first inference rule that matches both the target's
      (dependent's) suffix (which may be null) and a file which matches the
      other suffix of the rule.	 Since it conducts this search by going
      through the list of .SUFFIXES values front to back, the order in which
      .SUFFIXES is defined is significant.

      To print out the rules compiled into the make on any machine, type:

	   make -fp - 2>&gt&gt&gt;/dev/null <&lt&lt&lt;/dev/null

      Since make defines an inference rule .c.o, the example in the General
      Description section can be rewritten more simply:

	   OBJS = a.o b.o
	       pgm: $(OBJS)
		   cc $(OBJS) -o pgm
	       $(OBJS): incl.h

      If a target or dependent name contains parentheses, it is assumed to
      be an archive library, the string within parentheses referring to a
      member within the library.  Thus lib(file.o) and $(LIB)(file.o) both
      refer to an archive library that contains file.o (this assumes the LIB
      macro has been previously defined).  The expression $(LIB)(file1.o
      file2.o) is not valid.  Rules pertaining to archive libraries have the
      form .xx.a where xx is the suffix from which the archive member is to
      be made.	An unfortunate byproduct of the current implementation
      requires the xx to be different from the suffix of the archive member.
      Thus, one cannot have lib(file.o) depend upon file.o explicitly.	The
      most common use of the archive interface follows.	 Here, we assume the
      source files are all C type source:

	   lib: lib(file1.o) lib(file2.o) lib(file3.o)
		@echo lib is now up-to-date
		$(CC) -c $(CFLAGS) $<&lt&lt&lt;
		ar rv $@ $*.o
		rm -f $*.o

      (See the section on Built-in Macros for an explanation of the <&lt&lt&lt;, @,
      and * symbols.) In fact, the .c.a rule listed above is built into make
      and is unnecessary in this example.  This rule is applied to each
      dependent of lib in turn.	 The following example accomplishes this
      more efficiently:

	   lib:	 lib(file1.o) lib(file2.o) lib(file3.o)
		$(CC) -c $(CFLAGS) $(?:.o=.c)
		ar rv lib $?
		rm $?
		@echo lib is now up-to-date

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 make(1)							     make(1)

      Here substitution in the macros is used.	The $?	list is defined to
      be the set of object file names (inside lib) whose C source files are
      out-of-date.  The substitution sequence translates the .o to .c.
      (Unfortunately, one cannot as yet transform to .c~; however, this may
      become possible in the future.) Note also, the disabling of the .c.a
      rule, which would have created and archived each object file, one by
      one.  This particular construct speeds up archive library maintenance
      considerably, but becomes very cumbersome if the archive library
      contains a mix of assembly programs and C programs.

      Archive members containing the definition of a symbol are designated
      by double parentheses around the symbol name, lib((entry_name)), but
      are otherwise handled as described above.

    Built-In Targets
      make has knowledge about some special targets.  These must be
      specified in the makefile to take effect (with the exception of
      .SUFFIXES, which is automatically set by make but can be changed by
      the user).

	   .DEFAULT	  If a file must be made but there are no explicit
			  commands or relevant built-in rules for it, the
			  commands associated with the target name .DEFAULT
			  are used if .DEFAULT has been defined in the
			  makefile.  .DEFAULT does not have any explicit

	   .PRECIOUS	  Dependents of this target are not removed when

	   .SILENT	  Same effect as the -s option.	 No dependents or
			  explicit commands need to be specified.

	   .IGNORE	  Same effect as the -i option.	 No dependents or
			  explicit commands need to be specified.

	   .SUFFIXES	  The explicit dependents of .SUFFIXES are added to
			  the built-in list of known suffixes and are used
			  in conjunction with the inference rules.  If
			  .SUFFIXES does not have any dependents, the list
			  of known suffixes is cleared.	 There are no
			  commands associated with .SUFFIXES.

	   .MUTEX	  Serialize the updating of specified targets (See
			  the Parallel Make Section).

    Built-in Macros
      There are five internally maintained macros that are useful for
      writing rules for building targets.  In order to clearly define the
      meaning of these macros, some clarification of the terms target and

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 make(1)							     make(1)

      dependent is necessary.  When make updates a target, it may actually
      generate a series of targets to update.  Before any rule (either
      explicit or implicit) is applied to the target to update it, recursion
      takes place on each dependent of the target.  The dependent, upon
      recursion, becomes a target itself, and may have or generate its own
      dependents, which in turn are recursed upon until a target is found
      that has no dependents, at which point the recursion stops.  Not all
      targets processed by make appear as explicit targets in the makefile;
      some of them are explicit dependents from the makefile while others
      are implicit dependents generated as make recursively updates the
      target.  For instance, when the following makefile is executed:

	   pgm:	 a.o b.o
	       cc a.o b.o -o pgm

      the following series of targets to be made is generated:

	   --- pgm   with two dependents and an explicit rule to follow

	   --- a.o   (recursively) with an implicit dependent of a.c which
		     matches the implicit rule .c.o

	   --- a.c   (recursively) with no implicit dependents and no
		     implicit rules.  This stops the recursion and simply
		     returns the last modification time of the file a.c.

	   --- b.o   (recursively) with an implicit dependent of b.c which
		     matches the implicit rule .c.o

	   --- b.c   (recursively) with no implicit dependents and no
		     implicit rules.  This stops the recursion and merely
		     returns the last modification time of the file b.c.

      In the definitions below, the word target refers to a target specified
      in the makefile, an explicit dependent specified in the makefile which
      becomes the target when make recurses on it, or an implicit dependent
      (generated as a result of locating an inference rule and file that
      match the suffix of the target) which becomes the target when make
      recurses on it.  The word dependent refers to an explicit dependent
      specified in the makefile for a particular target, or an implicit
      dependent generated as a result of locating an appropriate inference
      rule and corresponding file that matches the suffix of the target.

      It may be helpful to think of target rules as user specified rules for
      a particular target name, and inference rules as user or make
      specified rules for a particular class of target names.  It may also
      be helpful to remember that the value of the target name and its
      corresponding dependent names change as make recurses on both explicit
      and implicit dependents, and that inference rules are only applied to
      implicit dependents or to explicit dependents which do not have target
      rules defined for them in the makefile.

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      $@	     The $@ macro is the full target name of the current
		     target, or the archive filename part of a library
		     archive target.  It is evaluated for both target and
		     inference rules.

      $%	     The $% macro is only evaluated when the current target
		     is an archive library member of the form
		     libname(member.o) or libname((entry)).  In these cases,
		     $@ evaluates to libname and $% evaluates to member.o or
		     the object file containing the symbol entry.  $% is
		     evaluated for both target and inference rules.

      $?	     The $?  macro is the list of dependents that are out-
		     of-date with respect to the current target;
		     essentially, those modules that have been rebuilt.	 It
		     is evaluated for both target and inference rules, but
		     is usually only used in target rules.  $?	evaluates to
		     one name only in an inference rule, but may evaluate to
		     more than one name in a target rule.

      $<&lt&lt&lt;	     In an inference rule, $<&lt&lt&lt; evaluates to the source file
		     name that corresponds to the implicit rule which
		     matches the suffix of the target being made.  In other
		     words, it is the file that is out-of-date with respect
		     to the target.  In the .DEFAULT rule, the $<&lt&lt&lt; macro
		     evaluates to the current target name.  $<&lt&lt&lt; is evaluated
		     only for inference rules.	Thus, in the .c.o rule, the
		     $<&lt&lt&lt; macro would evaluate to the .c file.  An example for
		     making optimized .o files from .c files is:

			      cc -c -O $*.c


			      cc -c -O $<&lt&lt&lt;

      $*	     The macro $* is the current target name with the suffix
		     deleted.  It is evaluated only for inference rules.

      These five macros can have alternative forms.  When an uppercase D or
      F is appended to any of the five macros, the meaning is changed to
      ``directory part'' for D and ``file part'' for F.	 Thus, $(@D) refers
      to the directory part of the string $@.  If there is no directory
      part, ./ is generated.  When the $?  macro contains more than one
      dependent name, the $(?D) expands to a list of directory name parts
      and the $(?F) expands to a list of the filename parts.

      In addition to the built-in macros listed above, other commonly used
      macros are defined by make.  These macros are used in the default

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      inference rules, and can be displayed with the -p option.	 These
      macros can be used in target rules in the makefile.  They can also be
      redefined in the makefile.

	   $$@		  The $$@ macro has meaning only on dependency
			  lines.  Macros of this form are called dynamic
			  dependencies because they are evaluated at the
			  time the dependency is actually processed.  $$@
			  evaluates to exactly the same thing as $@ does on
			  a command line; i.e., the current target name.
			  This macro is useful for building large numbers of
			  executable files, each of which has only one
			  source file.	For instance, the following HP-UX
			  commands could all be built using the same rule:

			       CMDS = cat echo cmp chown
			       $(CMDS) : $$@.c
				   $(CC) -O $? -o $@

			  If this makefile is invoked with make cat echo cmp
			  chown, make builds each target in turn using the
			  generic rule, with $$@ evaluating to cat while cat
			  is the target, to echo when the target is echo,
			  and so forth.

			  The dynamic dependency macro can also take the F
			  form, $$(@F) which represents the filename part of
			  $$@.	This is useful if the targets contain
			  pathnames.  For example:

			       INCDIR = /usr/include
			       INCLUDES = $(INCDIR)/stdio.h \
				       $(INCDIR)/pwd.h	 \
				       $(INCDIR)/dir.h	 \
			       $(INCLUDES) : $$(@F)
				   cp $? $@
				   chmod 0444 $@

    Special Macros
      The VPATH macro allows make to search a colon separated list of
      directories for dependents.  Lines of the form VPATH= path1:path2 ...
      causes make to first search the current directory for a dependent and
      if the dependent is not found, make searches path1 and continues until
      the directories specified in the VPATH macro are exhausted.

    Environment Variables
      LANG provides a default value for the internationalization variables
      that are unset or null. If LANG is unset or null, the default value of
      "C" (see lang(5)) is used. If any of the internationalization

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      variables contains an invalid setting, make will behave as if all
      internationalization variables are set to "C".  See environ(5).

      LC_ALL If set to a non-empty string value, overrides the values of all
      the other internationalization variables.

      LC_CTYPE determines the interpretation of text as single and/or
      multi-byte characters, the classification of characters as printable,
      and the characters matched by character class expressions in regular

      LC_MESSAGES determines the locale that should be used to affect the
      format and contents of diagnostic messages written to standard error
      and informative messages written to standard output.

      NLSPATH determines the location of message catalogues for the
      processing of LC_MESSAGES.

      PROJECTDIR provides a directory to be used to search for SCCS files
      not found in the current directory. In all of the following cases, the
      search for SCCS files will be made in the directory SCCS in the
      identified directory. If the value of PROJECTDIR begins with a slash,
      it is considered an absolute pathname; otherwise, the home directory
      of a user of that name is examined for a subdirectory src or source.
      If such a directory is found, it is used. Otherwise, the value is used
      as a relative pathname.

      If PROJECTDIR is not set or has a null value, the current directory is
      searched first, followed by a search in the SCCS directory in the
      current directory.

      The setting of PROJECTDIR affects all files listed in the remainder of
      this utility description for files with a component named SCCS.

    International Code Set Support
      Single and multi-byte character code sets are supported.

      make returns a 0 upon successful completion or a value greater than 0
      if an error occurred.  If the -q option is specified, make returns 0
      if the target was up-to-date and a value greater than 0 if the target
      was not up-to-date.

      The following example creates an executable file from a C source code
      file without a makefile, if program.c exists in the current directory:

	   make program

      The following example shows more than one makefile specified and some
      command line macros defined, and updates the first target in module1:

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	   make -f module1 -f module2 RELEASE=1.0 CFLAGS=-g

      The following example updates two targets in a default makefile
      currently residing in the current directory:

	   make clobber prog

      The following example updates the prog target in a specified makefile,
      allows environment variables to override any common variables in the
      makefile, clears the built-in suffix list and ignore the built-in
      rules, and outputs exhaustive debugging information:

	   make -erd -f module1 prog

      Be wary of any file (such as an include file) whose access,
      modification, and last change times cannot be altered by the make-ing
      process.	For example, if a program depends on an include file that in
      turn depends on another include file, and if one or both of these
      files are out-of-date, make tries to update these files each time it
      is run, thus unnecessarily re-makeing up-to-date files that are
      dependent on the include file.  The solution is to manually update
      these files with the touch command before running make (see touch(1)).

      Some commands return non-zero status inappropriately; use -i to
      overcome the difficulty.

      File names with the characters = : @ $ do not work.

      Built-in commands that are directly executed by the shell such as cd
      (see cd(1)), are ineffectual across new-lines in make.

      The syntax (lib(file1.o file2.o file3.o) is illegal.

      You cannot build lib(file.o) from file.o.

      The macro $(a:.o=.c~) does not work.

      Expanded target lines cannot contain more than 16384 characters,
      including the terminating new-line.

      If no makefile exists in the current directory, typing

	   make filename

      results in make attempting to build filename from filename.c

      If make is invoked in a shell script with a quoted argument that
      evaluates to NULL (such as $@), make fails.

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 make(1)							     make(1)

    NFS Warning:
      When comparing modification times of files located on different NFS
      servers, make behaves unpredictably if the clocks on the servers are
      not synchronized.


      cc_bundled(1), cd(1), lex(1), mkmf(1), sh(1), environ(5), lang(5),

      A Nutshell Handbook, Managing Projects With Make by Steve Talbot,
      Second Edition, O'Reilly & Associates, Inc., 1986.

      make: SVID2, SVID3, XPG2, XPG3, XPG4, POSIX.2

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